A 24-trit chip just woke computing from its 60-year binary coma
While the world obsesses over 3-nanometer nodes and trillion-trans GPUs, Claudio Lorenzo La Rosa has quietly booted a 24-trit ternary CPU on a $79 open-source FPGA, proving the road not taken in 1958 is still drivable.
The ghost of setun walks again
Moscow University built the original Setun in 1958; it consumed less power, needed fewer parts and ran circles around Soviet mainframes. The West yawned, doubled-down on binary, and buried the blueprints. La Rosa’s 5500FP is the first general-purpose ternary chip since that cold-war curiosity, etched in Verilog instead of germanium but speaking the same -1, 0, +1 dialect. Each trit packs 1.58× the information density of a bit, so a 24-trit word can encode what needs 38 bits in silicon that still thinks in on-off.
The trick is emulation: two ordinary binary gates fake one trit. It wastes transistors, yes, but it also means the prototype plugs into today’s motherboards without begging TSMC for a new process. Clock? A humble 20 MHz—your smart light bulb laughs. Yet the instruction set is complete: 120 opcodes, atomic read-modify-write, barrel shifter, even a pipelined multiplier. La Rosa has already booted a Forth interpreter; Mandelbrot renders in minutes, not frames, but it renders.
Why the industry locked the door in 1960
The transistor factories of 1962 had bet their mortgages on NAND and NOR; retooling for three voltage levels looked like economic suicide. History wrote the verdict before engineering could appeal. Knuth still calls balanced ternary “the most beautiful number system,” but beauty lost to the supply chain. The 5500FP doesn’t claim superiority; it reopens the case file. Signal-processing kernels, certain AI dot-product monsters and any workload that natively juggles signed integers hate two’s-complement overhead; they greet native negative numbers like long-lost siblings.
La Rosa, funded by Patreon and a Spanish research scraps grant, taped out the core on a Lattice iCE40. Total lab budget: less than the catering line for a single Intel stepping. He has now shipped the RTL to twenty universities; two Chinese teams are already porting LLVM.
Silicon dreams beyond the fpga sandbox
The roadmap is brutally simple: shrink the emulator, chase a 28-nm ternary cell library, then tape out a real die. A native ternary transistor would switch at three distinct carrier densities; simulations at Imec suggest a 40 % energy saving for the same integer throughput. No one is promising smartphones that speak trits next year, but niche chips—think neural inference, think cryptography, think extreme-radiation space nodes—could slip into the supply chain the same way FPGAs once did.
Binary won the last round because the fabs were ready, not because the math was sacred. The 5500FP reminds the industry that path dependence is not destiny. La Rosa’s next upload: a ternary matrix unit that beats a Raspberry Pi 5 on raw multiply-accumulate while drawing half the wattage. The code is GPL. The patents are zero. The clock is ticking; companies now have working hardware to test their risk on. If one foundry takes the bet, sixty years of “what-if” could become a shipping SKU before this decade is out.